[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"$f305tCDlbk2vi4FAthsKYUYlDmk_t11Q66tZDSykUtqs":3},{"id":4,"name":5,"category_id":6,"subcategory_id":7,"uploaded_by":8,"downloads":9,"size":10,"seeders":11,"leechers":12,"infohash":13,"language":14,"title":15,"slogan":15,"poster_alt":16,"description":15,"cover_image":15,"magnet_link":17,"stream_link":16,"content":18,"files":19,"comments_count":20,"tracker_list":21,"date_uploaded":22,"last_checked":23,"last_checked_at":16,"user_id":16,"submit_flag":20,"uploaded_at":24,"created_at":25,"updated_at":25,"slugged_title":26,"category_name":27,"subcategory_name":28,"uploaded_ago":29,"category":30,"subcategory":31,"comments":33},6622978,"Udemy - Xilinx VIVADO Beginner Course for FPGA Development in VHD...",9,34,"freecoursewb",35193,"2.2 GB",15290,10817,"182DA742E5FCAA72B89578A8A6BB39DFBE957B97","English","",null,"magnet:?xt=urn:btih:182DA742E5FCAA72B89578A8A6BB39DFBE957B97&dn=Udemy+-+Xilinx+VIVADO+Beginner+Course+for+FPGA+Development+in+VHDL&tr=udp%3A%2F%2Ftracker.torrent.eu.org%3A451%2Fannounce&tr=udp%3A%2F%2Ftracker.tiny-vps.com%3A6969%2Fannounce&tr=http%3A%2F%2Ftracker.foreverpirates.co%3A80%2Fannounce&tr=udp%3A%2F%2Ftracker.cyberia.is%3A6969%2Fannounce&tr=udp%3A%2F%2Fexodus.desync.com%3A6969%2Fannounce&tr=udp%3A%2F%2Fexplodie.org%3A6969%2Fannounce&tr=udp%3A%2F%2Ftracker.opentrackr.org%3A1337%2Fannounce&tr=udp%3A%2F%2F9.rarbg.to%3A2780%2Fannounce&tr=udp%3A%2F%2Ftracker.internetwarriors.net%3A1337%2Fannounce&tr=udp%3A%2F%2Fipv4.tracker.harry.lu%3A80%2Fannounce&tr=udp%3A%2F%2Fopen.stealth.si%3A80%2Fannounce&tr=udp%3A%2F%2F9.rarbg.to%3A2900%2Fannounce&tr=udp%3A%2F%2F9.rarbg.me%3A2720%2Fannounce&tr=udp%3A%2F%2Fopentor.org%3A2710%2Fannounce&tr=udp%3A%2F%2Ftracker.opentrackr.org%3A1337%2Fannounce&tr=http%3A%2F%2Ftracker.openbittorrent.com%3A80%2Fannounce&tr=udp%3A%2F%2Fopentracker.i2p.rocks%3A6969%2Fannounce&tr=udp%3A%2F%2Ftracker.internetwarriors.net%3A1337%2Fannounce&tr=udp%3A%2F%2Ftracker.leechers-paradise.org%3A6969%2Fannounce&tr=udp%3A%2F%2Fcoppersurfer.tk%3A6969%2Fannounce&tr=udp%3A%2F%2Ftracker.zer0day.to%3A1337%2Fannounce","\u003Cp>\u003Cstrong> Xilinx VIVADO Beginner Course for FPGA Development in VHDL  \u003C/strong>\n\u003Cbr/>\u003Cbr/>\u003Cspan style=\"font-size: 16px\">\u003Cstrong>\u003Ca href=\"https://WebToolTip.com\" target=\"_blank\">https://WebToolTip.com\u003C/a> \u003C/strong>\u003C/span>\n\u003Cbr/>\u003Cbr/>Last updated 5/2019\n\u003Cbr/>MP4 | Video: h264, 1920x1080 | Audio: AAC, 44.1 KHz, 2 Ch\n\u003Cbr/>Language: English | Duration: 5h 3m | Size: 2.23 GB\n\u003Cbr/>\u003Cbr/>Learn how to Create VHDL Design,Simulation Testbench & Implementation with Xilinx VIVADO & FPGA: from Basic to Advanced.\n\u003Cbr/>\u003Cbr/>What you'll learn\n\u003Cbr/>Idea of VHDL Programming , VIVADO Design Methodology and Designing/Implementing Design in Zynq FPGA-ZedBoard\n\u003Cbr/>Use fundamental VHDL constructs to create simple designs. Understanding the Conditional Statements in VHDL.\n\u003Cbr/>Design Simulation testbench on VHDL and simulating the designs.\n\u003Cbr/>Design with structural design methodology on VHDL.\n\u003Cbr/>Designing Decoder, Adder, Register and Counter in VHDL and Implementing in ZedBoard\n\u003Cbr/>Implementing State Machine in VHDL; Designing/Implementing Sequence Detector\n\u003Cbr/>\u003Cbr/>Requirements\n\u003Cbr/>Basic idea of VHDL\n\u003Cbr/>Idea of VIVADO Design Suit and Zynq 7000 Architecture\n\u003Cbr/>FPGA Design Methodology Basic\n\u003Cbr/>We have included all the basics of VHDL, VIVADO and Zynq in this Course, So No Worries!!!\u003C/p>","\u003Ch2>Files: \u003C/h2>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>[ WebToolTip.com ] Udemy - Xilinx VIVADO Beginner Course for FPGA Development in VHDL\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>Get Bonus Downloads Here.url (0.2 KB)\u003C/li>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>~Get Your Files Here !\u003C/span>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>1 - Section 1_Introduction and Overview of VHDL, VIVADO & Zynq\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>1. Introduction and Overview of VHDL (Description).html (1.6 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>1. Introduction and Overview of VHDL.mp4 (151.1 MB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>2. VHDL Data Types and Operators Overview with How to create user defined data type (Description).html (1.4 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>2. VHDL Data Types and Operators Overview with How to create user defined data type.mp4 (28.8 MB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>3. Section 1_0 How to Install Xilinx VIVADO and Get 30 day Evaluation License (Description).html (1.0 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>3. Section 1_0 How to Install Xilinx VIVADO and Get 30 day Evaluation License.mp4 (44.0 MB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-book\">\u003C/i>3. Section 1_0 How to download and install Xilinx VIVADO Design Suit and get 1 month free license_VIVADO.pdf (1.2 MB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>4. Section_1 Lab Nor Gate in VHDL with VIVADO on ZedBoard (Description).html (1.0 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>4. Section_1 Lab Nor Gate in VHDL with VIVADO on ZedBoard.mp4 (204.8 MB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>5. Nor Gate Implementation on ZedBoard FPGA (Optional) (Description).html (1.0 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>5. Nor Gate Implementation on ZedBoard FPGA (Optional).mp4 (33.6 MB)\u003C/li>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>section 1_ sources_ VHDL Programming with VIVADO and Zynq FPGA\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>nor_gate.vhd (1.0 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>nor_gate.xdc (0.5 KB)\u003C/li>\n\u003C/ul>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>10 - VHDL Reference Guide (From Basic Design to FSM Examples) from Digitronix Nepal\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>23. VHDL Reference Guide from Digitronix Nepal (Basic Gate to Sequential Circuits).html (76.4 KB)\u003C/li>\n\u003C/ul>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>11 - Bonus Lecture\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>24. What Next (Description).html (0.6 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>24. What Next.html (6.4 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>25. Books and Reference Links (Description).html (0.7 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>25. Books and Reference Links.html (8.0 KB)\u003C/li>\n\u003C/ul>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>2 - Simulating VHDL code with Testbench\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>6. Simulation Overview and Lab Simulation of NAND Gate in VIVADO (Description).html (1.1 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>6. Simulation Overview and Lab Simulation of NAND Gate in VIVADO.mp4 (180.4 MB)\u003C/li>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>section 2 sources_VHDL Programming with VIVADO and Zynq FPGA\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>nand_tb.vhd (1.0 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>nand_vhd.vhd (1.0 KB)\u003C/li>\n\u003C/ul>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>3 - Conditional Statements in VHDL\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>7. Lecture Conditional Statement in VHDL (Description).html (1.0 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>7. Lecture Conditional Statement in VHDL.mp4 (110.8 MB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>8. Section 3_2 Lab 31 Decoder Design and Implementation on ZedBoard (Description).html (1.0 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>8. Section 3_2 Lab 31 Decoder Design and Implementation on ZedBoard.mp4 (170.2 MB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>9. Section 3_3 Lab 31 Decoder Demo (Description).html (1.0 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>9. Section 3_3 Lab 31 Decoder Demo.mp4 (29.7 MB)\u003C/li>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>section 3 sources_VHDL Programming with VIVADO and Zynq FPGA\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>Section 3_2_decoder_2 4.vhd (0.6 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>Section 3_2_decoder_2 4_tb.vhd (0.9 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-images\">\u003C/i>decoder 2_4.png (173.2 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-images\">\u003C/i>simulation of decoder 2 is to 4 in ise vhdl.PNG (24.5 KB)\u003C/li>\n\u003C/ul>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>4 - Section 4_A Combinational Circuit Design(Half Adder Design) with VHDL in VIVADO\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>10. Section 4_1 Combinational Circuit Design in VHDL (Description).html (1.2 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>10. Section 4_1 Combinational Circuit Design in VHDL.mp4 (105.8 MB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>11. Section 4_2 Lab41 Half Adder Design and Implementation with VIVADO and Zynq (Description).html (0.9 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>11. Section 4_2 Lab41 Half Adder Design and Implementation with VIVADO and Zynq.mp4 (123.6 MB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>12. Half Adder Implementation on ZedBoard Demo.mp4 (29.7 MB)\u003C/li>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>section 4 sources_VHDL Programming with VIVADO and Zynq FPGA\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>section 4 Lab 41 half_adder.vhd (0.2 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>section 4 Lab 42 Full_adder.vhd (0.3 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>section 4 comparator.vhd (1.0 KB)\u003C/li>\n\u003C/ul>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>5 - Section 4_B Seven Segment Decoder Design and Display Interfacing on VHDL\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>13. Seven Segment Decoder Design in VHDL (Description).html (0.7 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>13. Seven Segment Decoder Design in VHDL.html (24.4 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-book\">\u003C/i>13. Seven Segment Display with Nexys 2.pdf (477.8 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-book\">\u003C/i>13. Seven Segment Display_4_digit with Nexys 2_V2.pdf (361.2 KB)\u003C/li>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>Sources\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>clkdiv.vhd (1.7 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>fsm.vhd (1.8 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>mux44.vhd (2.0 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>seven_seg_driver.vhd (2.5 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>seven_segment.vhd (1.6 KB)\u003C/li>\n\u003C/ul>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>6 - Section 5 Structural Design with VHDL (Full Adder Design using Half Adder)\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>14. Section 5 Structural Design with VHDL with Lab on Designing Full Adder using Hal (Description).html (1.1 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>14. Section 5 Structural Design with VHDL with Lab on Designing Full Adder using Hal.mp4 (230.0 MB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>15. Section 5 Lab 51 Structural Design Lab for Full Adder Demo (Description).html (1.6 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>15. Section 5 Lab 51 Structural Design Lab for Full Adder Demo.mp4 (41.4 MB)\u003C/li>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>section 5 sources_VHDL Programming with VIVADO and Zynq FPGA\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>Full_Adder.vhd (0.6 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>full_adder_tb.vhd (2.7 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>half_adder.vhd (0.3 KB)\u003C/li>\n\u003C/ul>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>7 - Section 6 Sequential Circuit Design (BCD Counter Design & Implement) with VHDL\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>16. Section 6_1 Sequential Circuit Design in VHDL (Description).html (1.0 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>16. Section 6_1 Sequential Circuit Design in VHDL.mp4 (115.7 MB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>17. Section 6_2 Lab 61 BCD Counter Design and Implementation (Description).html (1.4 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>17. Section 6_2 Lab 61 BCD Counter Design and Implementation.mp4 (146.9 MB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>18. BCD Counter Implementation on ZedBoard Demo.mp4 (21.1 MB)\u003C/li>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>section 6 sources_VHDL Programming with VIVADO and Zynq FPGA\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>bcd_vhd.vhd (1.4 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>bcd_xdc.xdc (0.7 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>section 6_1 3 bit shift register.vhd (0.8 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>section 6_1 D Flipflop.vhd (0.7 KB)\u003C/li>\n\u003C/ul>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>8 - Section 7 Finite State Machine Design Sequence Detector Design Implement in VHDL\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>19. Section 7 FSM Design in VHDL Lab 71 Sequence Detector Design (Description).html (1.5 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>19. Section 7 FSM Design in VHDL Lab 71 Sequence Detector Design.mp4 (143.8 MB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-book\">\u003C/i>19. VHDL_Reference_Guide_v3_Aug 2017 Prepared_by_Digitronix_Nepal.pdf (1.9 MB)\u003C/li>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>Section 7 State machine design sequence detector_VHDL Programming with VIVADO and Zynq FPGA\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>seq_det.xdc (0.9 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>seq_det_tb.vhd (2.6 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-other-file\">\u003C/i>seq_det_vhdl.vhd (1.1 KB)\u003C/li>\n\u003C/ul>\n\u003Cspan class=\"head\">\u003Ci class=\"flaticon-folder\">\u003C/i>9 - ALU Design (8 bit & N bit ALU Design with Wallace Tree Multiplication Algorithm)\u003C/span>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>20. ALU Design (ALU Overview and 8 Bit ALU Design)-I (Description).html (0.8 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>20. ALU Design (ALU Overview and 8 Bit ALU Design)-I.mp4 (101.8 MB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>21. ALU Design (ALU Overview and 8 Bit ALU Design)-II (Description).html (0.8 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>21. ALU Design (ALU Overview and 8 Bit ALU Design)-II.mp4 (27.3 MB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-script\">\u003C/i>22. ALU Design Lab 81 N bit ALU Design (Description).html (0.7 KB)\u003C/li>\n\u003Cli>\u003Ci class=\"flaticon-movies\">\u003C/i>22. ALU Design Lab 81 N bit ALU Design.mp4 (236.5 MB)\u003C/li>\n\u003C/ul>\n\u003Cul>\n\u003Cli>\u003Ci class=\"flaticon-book\">\u003C/i>Bonus Resources.txt (0.1 KB)\u003C/li>\n\u003C/ul>\u003C/ul>\u003C/ul>\u003C/ul>\u003C/ul>\u003C/ul>\u003C/ul>\u003C/ul>\u003C/ul>\u003C/ul>",0,"\u003Ch3>Code: \u003C/h3>\n\u003Cul>\n\u003Cli>\u003Cspan class=\"icon\">\u003Ci class=\"flaticon-href-link\">\u003C/i>\u003C/span> udp://tracker.torrent.eu.org:451/announce\u003C/li>\n\u003Cli>\u003Cspan class=\"icon\">\u003Ci class=\"flaticon-href-link\">\u003C/i>\u003C/span> udp://tracker.tiny-vps.com:6969/announce\u003C/li>\n\u003Cli>\u003Cspan class=\"icon\">\u003Ci class=\"flaticon-href-link\">\u003C/i>\u003C/span> http://tracker.foreverpirates.co:80/announce\u003C/li>\n\u003Cli>\u003Cspan class=\"icon\">\u003Ci class=\"flaticon-href-link\">\u003C/i>\u003C/span> udp://tracker.cyberia.is:6969/announce\u003C/li>\n\u003Cli>\u003Cspan class=\"icon\">\u003Ci class=\"flaticon-href-link\">\u003C/i>\u003C/span> udp://exodus.desync.com:6969/announce\u003C/li>\n\u003Cli>\u003Cspan class=\"icon\">\u003Ci class=\"flaticon-href-link\">\u003C/i>\u003C/span> udp://explodie.org:6969/announce\u003C/li>\n\u003Cli>\u003Cspan class=\"icon\">\u003Ci class=\"flaticon-href-link\">\u003C/i>\u003C/span> udp://tracker.opentrackr.org:1337/announce\u003C/li>\n\u003Cli>\u003Cspan class=\"icon\">\u003Ci class=\"flaticon-href-link\">\u003C/i>\u003C/span> udp://9.rarbg.to:2780/announce\u003C/li>\n\u003Cli>\u003Cspan class=\"icon\">\u003Ci class=\"flaticon-href-link\">\u003C/i>\u003C/span> udp://tracker.internetwarriors.net:1337/announce\u003C/li>\n\u003Cli>\u003Cspan class=\"icon\">\u003Ci class=\"flaticon-href-link\">\u003C/i>\u003C/span> udp://ipv4.tracker.harry.lu:80/announce\u003C/li>\n\u003Cli>\u003Cspan class=\"icon\">\u003Ci class=\"flaticon-href-link\">\u003C/i>\u003C/span> udp://open.stealth.si:80/announce\u003C/li>\n\u003Cli>\u003Cspan class=\"icon\">\u003Ci class=\"flaticon-href-link\">\u003C/i>\u003C/span> udp://9.rarbg.to:2900/announce\u003C/li>\n\u003Cli>\u003Cspan class=\"icon\">\u003Ci class=\"flaticon-href-link\">\u003C/i>\u003C/span> udp://9.rarbg.me:2720/announce\u003C/li>\n\u003Cli>\u003Cspan class=\"icon\">\u003Ci class=\"flaticon-href-link\">\u003C/i>\u003C/span> udp://opentor.org:2710/announce\u003C/li>\n\u003C/ul>","1 day ago","2 hours ago","2026-04-10 20:46:19","2026-04-10T20:46:19.000000Z","udemy-xilinx-vivado-beginner-course-for-fpga-development-in-vhd","Other","Tutorials","Apr. 10th '26",{"id":6,"name":27},{"id":7,"name":28,"icon":32},"flaticon-tutorial",[]]